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1 for more information www.linear.com/lt3753 typical a pplica t ion fea t ures descrip t ion active clamp synchronous forward controller the lt ? 3753 is a current mode pwm controller optimized for an active clamp forward converter topology, allowing up to 100v input operation. a programmable volt-second clamp allows primary switch duty cycles above 50% for high switch, transformer and rectifier utilization. active clamp control reduces switch voltage stress and increases efficiency. a synchronous output is available for controlling secondary side syn - chronous rectification. the lt3753 is available in a 38-lead plastic tssop pack - age with missing pins for high voltage spacings. 36v to 72v, 5v/20a active clamp isolated forward converter a pplica t ions n input voltage range: 8.5v to 100v n programmable volt-second clamp n high efficiency control: active clamp, synchronous rectification, programmable delays n short-circuit (hiccup mode) overcurrent protection n programmable soft-start/stop n programmable ovlo and uvlo with hysteresis n programmable frequency (100khz to 500khz) n synchronizable to an external clock n industrial, automotive and military systems n 48v telecommunication isolated power supplies l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. 44.2k 1.87k 14.7k 57.6k 30.1k 100k 100k v + gnd-f gnd-s coll 3.3nf 34.8k ref lt1431 1k 0.012 10k 100 ps2801-1 1k 2.2nf 250v 1f 22nf 4.7f 25v 1f 10v 22f 10v 1k v out 47f 10v v out 5v 20a 560f 10v 3753 ta01 1f t ao t as t os t blnk ivsec rt ss1 ss2 fb comp intv cc sout i sensen i sensep out v in aout oc 1.96k 105k uvlo_v sec lt3753 sync 100nf irf6217 9:2 68nf 250v bsc0902nsi bsc0902nsi bsc190n15ns3 3.3h 137k 137k + ?? 4.7f 100v 3 v in 36v to 72v gnd ovlo 100 4.7nf 250v 0.22f 200 5 5 lt3753 3753f
2 for more information www.linear.com/lt3753 table o f c on t en t s features ..................................................... 1 applications ................................................ 1 t ypical application ........................................ 1 description .................................................. 1 table of contents .......................................... 2 absolute maximum ratings .............................. 3 order information .......................................... 3 pin configuration .......................................... 3 electrical characteristics ................................. 4 t ypical performance characteristics ................... 7 pin functions .............................................. 10 block diagram ............................................. 11 t iming diagrams ......................................... 12 operation ................................................... 14 introduction ....................................................... 14 p art start-up ...................................................... 14 applications information ................................ 15 p rogramming system input undervoltage lockout (uvlo) threshold and hysteresis ......... 15 so ft-stop shutdown ........................................... 15 m icropower shutdown ....................................... 15 p rogramming system input overvoltage lockout (ovlo) threshold ................................. 15 p rogramming switching frequency .................... 16 s ynchronizing to an external clock .................... 16 in tv cc regulator bypassing and operation ...... 16 ad aptive leading edge blanking plus programmable extended blanking...................... 17 current sensing and programmable slope compensation .................................................... 18 o vercurrent: hiccup mode .................................. 18 p rogramming maximum duty cycle clamp: d vsec (volt-second clamp) ................................ 18 d vsec open loop control: no opto-coupler, error amplifier or reference ............................... 19 r ivsec : open pin detection provides safety ....... 19 tr ansformer reset: active clamp technique ..... 20 l o side active clamp topology (lt3753)........... 20 hi side active clamp topology (lt3752-1) ......... 22 a ctive clamp capacitor value and voltage ripple ................................................................. 22 a ctive clamp mosfet selection ........................ 23 p rogramming active clamp switch timing: aout to out (t ao ) and out to aout (t oa ) delays ................................................................. 24 p rogramming synchronous rectifier timing: sout to out (t so ) and out to sout (t os ) delays ................................................................. 24 s oft-start (ss1, ss2) ......................................... 25 s oft-stop (ss1) .................................................. 25 h ard-stop (ss1, ss2) ......................................... 26 o ut, aout, sout pulse-skipping mode ............ 27 ao ut timeout .................................................... 27 m ain transformer selection ............................... 27 ge nerating auxiliary supplies ............................. 28 pr imary-side auxiliary supply ............................ 29 s econdary-side auxiliary supply ....................... 29 p rimary-side power mosfet selection ............. 30 s ynchronous control (sout) ............................. 31 o utput inductor value ......................................... 32 o utput capacitor selection ................................. 32 i nput capacitor selection ................................... 32 p cb layout / thermal guidelines ...................... 33 package description ..................................... 35 t ypical application ....................................... 36 related parts .............................................. 36 lt3753 3753f
3 for more information www.linear.com/lt3753 p in c on f igura t ion a bsolu t e maxi m u m r a t ings v in .......................................................................... 100 v uvlo_v sec , ovlo .................................................... 2 0v intv cc , ss1 .............................................................. 16v f b, sync .................................................................... 6v s s2, comp, test1, rt ............................................... 3v i sensep , i sensen , oc, test2 .................................. 0.3 5v ivsec .................................................................. C 250a operating junction temperature range (notes 2, 3) lt 3753efe ......................................... C 40c to 125c l t3753ife .......................................... C 40c to 125c lt 3753hfe ........................................ C 40c to 150c lt 3753mpfe ..................................... C 55c to 150c storage temperature range .................. C 65c to 150c lead temperature (soldering, 10 sec) .................. 3 00c (note 1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 top view fe package variation: fe38(31) 38-lead plastic tssop 38 37 36 34 32 30 28 26 24 22 21 20 test1 nc rt fb comp sync ss1 ivsec unlo_v sec ovlo t ao t as t os t blnk nc nc ss2 gnd pgnd pgnd nc test2 nc aout sout v in intv cc out oc i sensep i sensen 39 pgnd gnd ja = 25c/w exposed pad (pin 39) is pgnd and gnd, must be soldered to pcb o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range lt3753efe#pbf lt3753efe#trpbf lt3753fe 38-lead plastic tssop C40c to 125c lt3753ife#pbf lt3753ife#trpbf lt3753fe 38-lead plastic tssop C40c to 125c lt3753hfe#pbf lt3753hfe#trpbf lt3753fe 38-lead plastic tssop C40c to 150c lt3753mpfe#pbf lt3753mpfe#trpbf lt3753fe 38-lead plastic tssop C55c to 150c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult ltc marketing for information on nonstandard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ lt3753 3753f
4 for more information www.linear.com/lt3753 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in = 12v, uvlo_v sec = 2.5v. parameter conditions min typ max units operational input voltage l 8.5 100 v v in(on) l 7.75 8.4 v v in(off) 7.42 v v in(on/off) hysteresis l 0.11 0.33 0.55 v v in quiescent current fb = 1.5v (not switching) 5.9 7.5 ma uvlo_v sec micropower threshold (v sd ) i vin < 20a l 0.2 0.4 0.6 v v in shutdown current (micropower) uvlo_v sec = 0.2v 20 40 a uvlo_v sec threshold (v sys_uv ) l 1.180 1.250 1.320 v v in shutdown current (after soft-stop) uvlo_v sec = 1v 165 220 a uvlo_v sec (on) current uvlo_v sec = v sys_uv + 50mv 0 a uvlo_v sec (off) current hysteresis current with one-shot communication current uvlo_v sec = v sys_uv C 50mv (note 13) l 4.0 5 25 6.0 a a ovlo (rising) (no switching, reset ss1) l 1.220 1.250 1.280 v ovlo (falling) (restart ss1) 1.215 v ovlo hysteresis l 23 35 47 mv ovlo pin current (note 10) ovlo = 0v ovlo = 1.5v (ss1 = 2.7v) ovlo = 1.5v (ss1 = 1.0v) 5 0.9 5 100 100 na ma na oscillator frequency: f osc = 100khz r t = 82.5k 94 100 106 khz frequency: f osc = 300khz r t = 24.9k l 279 300 321 khz frequency: f osc = 500khz r t = 13.7k 470 500 530 khz f osc line regulation r t = 24.9k, 8.5v < v in < 100v 0.05 0.1 %/v frequency and d vsec foldback ratio (fold) ss1 = v ssact + 25mv, ss2 = 2.7v 4 sync input high threshold (note 4) l 1.2 1.8 v sync input low threshold (note 4) l 0.6 1.025 v sync pin current sync = 6v 75 a sync frequency/programmed f osc 1.0 1.25 khz/khz linear regulator (intv cc ) intv cc regulation voltage 9.4 10 10.4 v dropout (v in -intv cc ) v in = 8.75v, i intvcc = 10ma 0.6 v intv cc uvlo(+) (start switching) 7 7.4 v intv cc uvlo(C) (stop switching) 6.8 7.2 v intv cc uvlo hysteresis 0.1 0.2 0.3 v intv cc ovlo(+) (stop switching) 15.9 16.5 17.2 v intv cc ovlo(C) (start switching) 15.4 16 16.7 v intv cc ovlo hysteresis 0.38 0.5 0.67 v intv cc current limit intv cc = 0v intv cc = 8.75v l 9.5 19 13 27 17 32 ma ma lt3753 3753f
5 for more information www.linear.com/lt3753 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in = 12v, uvlo_v sec = 2.5v. parameter conditions min typ max units error amplifier fb reference voltage l 1.220 1.250 1.275 v fb line reg 8.5v < v in < 100v 0.1 0.3 mv/v fb load reg comp_sw C 0.1v < comp < comp_v oh C 0.1v 0.1 0.3 mv/v fb input bias current (note 8) 50 200 na open-loop voltage gain 85 db unity-gain bandwidth (note 6) 2.5 mhz comp source current fb = 1v, comp = 1.75v (note 8) 6 11 ma comp sink current fb = 1.5v, comp = 1.75v 6.5 11.5 ma comp output high clamp fb = 1v 2.6 v comp switching threshold 1.25 v current sense i sensep maximum threshold fb = 1v, oc = 0v 180 220 260 mv comp current mode gain ?v comp /?v isensep 6.1 v/v i sensep input current (d = 0%) (note 8) 2 a i sensep input current (d = 80%) (note 8) 33 a i sensen input current fb = 1.5v (comp open) (note 8) fb = 1v (comp open) (note 8) 20 90 30 135 a a oc over current threshold l 82.5 96 107.5 mv oc input current 200 500 na aout driver (active clamp switch control) aout rise time c l = 1nf (note 5), intv cc = 12v 90 ns aout fall time c l = 1nf (note 5), intv cc = 12v 90 ns aout low level 0.1 v aout high level intv cc = 12v 11.9 v aout high level in shutdown uvlo_v sec = 0v, intv cc = 8v, i aout = 1ma out of the pin 7.8 v aout edge to out (rise): (t ao ) c sout = 1nf, c out = 3.3nf, intv cc = 12v r tao = 44.2k r tao = 73.2k (note 9) 168 253 218 328 268 403 ns ns out (fall) to aout edge: (t oa ) c sout = 1nf, c out = 3.3nf, intv cc = 12v r tao = 44.2k r tao = 73.2k (note 10) 150 214 196 295 250 376 ns ns sout driver (synchronous rectification control) sout rise time c out = 1nf, intv cc = 12v (note 5) 90 ns sout fall time c out = 1nf, intv cc = 12v (note 5) 90 ns sout low level 0.1 v sout high level intv cc = 12v 11.9 v sout high level in shutdown uvlo_v sec = 0v, intv cc = 8v, i sout = 1ma out of the pin 7.8 v aout edge to sout (fall): (t as ) c aout = c sout = 1nf, intv cc = 12v r tas = 44.2k (note 11) r tas = 73.2k 168 253 218 328 268 403 ns ns sout (fall) to out (rise): (t so = t ao C t as ) c sout = 1nf, c out = 3.3nf, intv cc = 12v r tao = 73.2k, r tas = 44.2k (notes 9, 11) r tao = 44.2k, r tas = 73.2k 70 C70 110 C110 132 C132 ns ns lt3753 3753f
6 for more information www.linear.com/lt3753 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in = 12v, uvlo_v sec = 2.5v. parameter conditions min typ max units out (fall) to sout (rise): (t os ) c sout = 1nf, c out = 3.3nf, intv cc = 12v r tos = 14.7k r tos = 44.2k (note 12) 52 102 68 133 84 164 ns ns out driver (main power switch control) out rise time c out = 3.3nf, intv cc = 12v (note 5) 19 ns out fall time c out = 3.3nf, intv cc = 12v (note 5) 20 ns out low level 0.1 v out high level intv cc = 12v 11.9 v out low level in shutdown uvlo_v sec = 0v, intv cc = 12v, i out = 1ma into the pin 0.25 v out (volt-sec) max duty cycle clamp d vsec (1 ? system input (min)) 100 d vsec (2 ? system input (min)) 100 d vsec (4 ? system input (min)) 100 r t = 22.6k, r ivsec = 51.1k, fb = 1v, ss1 = 2.7v uvlo_v sec = 1.25v uvlo_v sec = 2.50v uvlo_v sec = 5.00v 68.5 34.3 17.5 72.5 36.5 18.6 76.2 38.7 19.7 % % % out minimum on t ime c out = 3.3nf, intv cc = 12v (note 7) r tblnk = 14.7k r tblnk = 73.2k (note 14) 325 454 ns ns ss1 pin (soft-start: frequency and d vsec ) (soft-stop: comp pin, frequency and d vsec ) ss1 reset threshold (v ss1(rth) ) 150 mv ss1 active threshold (v ss1(act) ) (allow switching) 1.25 v ss1 charge current (soft-start) ss1 = 1.5v (note 8) 7 11.5 16 a ss1 discharge current (soft-stop) ss1 = 1v, uvlo_v sec = v sys_uv C 50mv 6.4 10.5 14.6 a ss1 discharge current (hard stop) oc > oc threshold intv cc < intv cc uvlo(C) ovlo > ovlo(+) ss1 = 1v 0.9 0.9 0.9 ma ma ma ss2 pin (soft-start: comp pin) ss2 discharge current ss1 < v ss(act) , ss1 = 2.5v 2.8 ma ss2 charge current ss1 > v ss(act) , ss1 = 1.5v 11 21 28 a note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the lt3753efe is guaranteed to meet performance specifications from 0c to 125c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the lt3753ife is guaranteed to meet performance specifications from C40c to 125c junction temperature. the lt3753hfe is guaranteed to meet performance specifications from C40c to 150c junction temperature. the lt3753mpfe is tested and guaranteed to meet performance specifications from C55c to 150c junction temperature. note 3: for maximum operating ambient temperature, see the thermal calculations section in the applications information section. note 4: sync minimum and maximum thresholds are guaranteed by sync frequency range test using a clock input with guard banded sync levels of 0.7v low level and 1.7v high level. note 5: rise and fall times are measured between 10% and 90% of gate driver supply voltage. note 6: guaranteed by design. note 7: on times are measured between rising and falling edges at 50% of gate driver supply voltage. note 8: current flows out of pin. note 9: guaranteed by correlation to r tas = 73.2k test. note 10: t oa timing guaranteed by design based on correlation to measured t ao timing. note 11: guaranteed by correlation to r tao = 44.2k test. note 12: guaranteed by correlation to r tos = 14.7k test. note 13: a 2s one-shot of 20a from the uvlo_v sec pin allows communication between ics to begin shutdown (useful when stacking supplies for more power ( = inputs in parallel/outputs in series)). the current is tested in a static test mode. the 2s one-shot is guaranteed by design. note 14: guaranteed by correlation to r tblnk = 14.7k test. lt3753 3753f
7 for more information www.linear.com/lt3753 v in shutdown current vs junction temperature v in(on) , v in(off) thresholds vs junction temperature v in quiescent current vs junction temperature uvlo_vsec turn-on threshold vs junction temperature uvlo_v sec hysteresis current vs junction temperature typical p er f or m ance c harac t eris t ics t a = 25c, unless otherwise noted. junction temperature (c) ?75 intv cc (v) 10.0 9.5 9.0 8.5 7.5 8.0 5.5 7.0 6.5 6.0 5.0 25 150 ?25 100 3753 g06 175 0 125 ?50 50 75 i load = 0ma i load = 10ma i load = 15ma i load = 20ma v in = 12v junction temperature (c) ?75 intv cc uvlo thresholds (v) 7.20 7.15 7.10 7.05 6.65 7.00 6.95 6.90 6.85 6.80 6.75 6.70 6.60 25 150 ?25 100 3753 g07 175 0 125 ?50 50 75 intv cc < uvlo (?): disable forward converter switching intv cc > uvlo (+): enable forward converter switching junction temperature (c) ?75 intv cc (v) 10.00 9.95 9.90 9.85 9.80 9.65 9.75 9.70 9.40 9.60 9.55 9.50 9.45 25 150 ?25 100 3753 g08 175 0 125 ?50 50 75 i load = 0ma i load = 10ma i load = 20ma i load = 30ma v in = 12v intv cc in dropout at v in = 8.75v vs current, junction temperature intv cc uvlo thresholds vs junction temperature intv cc regulation voltage vs current, junction temperature ss1 soft-start/soft-stop pin currents vs junction temperature junction temperature (c) ?75 ss1 currents (a) 14.0 13.5 13.0 12.5 8.5 12.0 11.5 11.0 10.5 10.0 9.5 9.0 8.0 25 150 ?25 100 3753 g09 175 0 125 ?50 50 75 ss1 soft-start: charge current* (?1) ss1 soft-stop: discharge current junction temperature (c) ?75 v in current (a) 40 30 20 10 0 25 150 ?25 100 3753 g01 175 0 125 ?50 50 75 v in = 12v, uvlo_vsec = 0.2v junction temperature (c) ?75 v in on/off thresholds (v) 9.0 8.5 8.0 7.5 7.0 6.5 6.0 25 150 ?25 100 3753 g02 175 0 125 ?50 50 75 vin_on vin_off junction temperature (c) ?75 v in i q (ma) 8 7 6 5 4 25 150 ?25 100 3753 g03 175 0 125 ?50 50 75 v in = 12v, no switching junction temperature (c) ?75 uvlo_vsec threshold (v) 1.275 1.270 1.265 1.260 1.255 1.250 1.245 1.240 1.235 1.230 1.225 25 150 ?25 100 3753 g04 175 0 125 ?50 50 75 junction temperature (c) ?75 uvlo_vsec hysteresis current (a) 6.0 5.5 5.0 4.5 4.0 25 150 ?25 100 3753 g05 175 0 125 ?50 50 75 lt3753 3753f
8 for more information www.linear.com/lt3753 ss1 high, active and reset levels vs junction temperature ss2 soft-start charge current vs junction temperature typical p er f or m ance c harac t eris t ics t a = 25c, unless otherwise noted. switching frequency vs ss1 pin voltage switching frequency vs junction temperature fb reference voltage vs junction temperature junction temperature (c) ?75 ss1 high, active and reset levels (v) 3.00 2.75 2.50 2.25 0.25 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0 25 150 ?25 100 3753 g10 175 0 125 ?50 50 75 ss1 active level (allow forward converter switching) ss1 high level ss1 reset level (reset ss1 latch) junction temperature (c) ?75 ss2 soft-start charge current (a) 25 24 23 16 22 21 20 19 18 17 15 25 150 ?25 100 3753 g11 175 0 125 ?50 50 75 ss2 pin current* (?1) junction temperature (c) ?75 switching frequency (khz) 325 320 315 280 310 305 300 295 290 285 275 25 150 ?25 100 3753 g13 175 0 125 ?50 50 75 r t = 24.9k junction temperature (c) ?75 fb reference voltage (v) 1.30 1.29 1.28 1.21 1.27 1.26 1.25 1.24 1.23 1.22 1.20 25 150 ?25 100 3753 g14 175 0 125 ?50 50 75 comp (v) 1.2 i sensep threshold (mv) 240 220 200 20 180 160 140 120 60 100 80 40 0 2.42.2 3753 g15 2.6 1.61.4 1.8 2 oc threshold duty cycle (%) 0 i sensep maximum threshold - vslope (v) 240 220 200 180 160 140 9080 3753 g16 100 2010 30 40 50 60 70 r islp = 0 vslp = i(i sensep ) ? r islp r islp = 1.5k r islp = 2k junction temperature (c) ?75 oc overcurrent threshold (mv) 110 105 100 85 95 90 80 25 150 ?25 100 3753 g17 175 0 125 ?50 50 75 i sensep maximum threshold vs comp i sensep maximum threshold C vslp vs duty cycle (programming slope compensation) oc overcurrent (hiccup mode) threshold vs junction temperature ss1 (v) 0 switching frequency (khz) 350 325 300 275 25 250 225 200 175 150 100 75 125 50 0 1 2.25 2.5 0.5 1.75 3753 g12 2.75 0.75 2 0.25 1.25 1.5 r t = 24.9k lt3753 3753f
9 for more information www.linear.com/lt3753 typical p er f or m ance c harac t eris t ics t a = 25c, unless otherwise noted. sout (fall) to out (rise) delay (t so = t ao C t as ) vs junction temperature out (fall) to sout (rise) delay (t os ) vs junction temperature extended blanking duration vs junction temperature aout to sout delay (t as ) vs junction temperature aout to out delay (t ao ) and out to aout delay (t oa ) vs junction temperature required r ivsec vs switching frequency (for d vsec 100 = 72.5%, uvlo_vsec = 1.25v) out pin rise/fall times vs out pin load capacitance out maximum duty cycle clamp (d vsec ) vs uvlo_v sec junction temperature (c) ?75 extended blanking duration (ns) 220 200 180 100 80 160 140 120 60 25 150 ?25 100 3753 g18 175 0 125 ?50 50 75 r tblnk = 73.2k r tblnk = 14.7k junction temperature (c) ?75 t ao and t ca (ns) 340 300 320 280 200 180 160 260 240 220 140 25 150 ?25 100 3753 g19 175 0 125 ?50 50 75 r tao = 73.2k t ao r tao = 44.2k t oa t ao t oa junction temperature (c) ?75 t as (ns) 340 300 320 280 200 180 160 260 240 220 140 25 150 ?25 100 3753 g20 175 0 125 ?50 50 75 r tas = 73.2k r tas = 44.2k junction temperature (c) ?75 t so (ns) 120 80 100 60 ?20 ?40 ?60 ?80 ?100 40 20 0 ?120 25 150 ?25 100 3753 g21 175 0 125 ?50 50 75 r tao = 73.2k, r tas = 44.2k r tao = 44.2k, r tas = 73.2k junction temperature (c) ?75 t so (ns) 160 140 80 60 40 120 100 20 25 150 ?25 100 3753 g22 175 0 125 ?50 50 75 r tos = 44.2k r tos = 14.7k r tos = 7.32k uvlo_vsec (v) 0 id vsec 100 (%) 80 70 40 30 20 10 60 50 0 3.75 8.757.5 3753 g23 10 2.51.25 5 6.25 v in = 12v r t = 24.9k (300khz) r ivsec = 51.1k switching frequency (khz) 100 programmed r ivsec (k) 160 140 80 60 40 20 120 100 0 250 450400 3753 g24 500 200150 300 350 out pin load capacitance (nf) 0 out pin rise/fall times (ns) 60 50 30 20 10 40 0 3 8 97 3753 g25 10 21 4 65 intv cc = 12v lt3753 3753f
10 for more information www.linear.com/lt3753 p in func t ions test1 (pin 1): connect to gnd. nc (pins 2, 15, 16, 34, 37): no connect pins. these pins are not connected inside the ic. these pins should be left open. rt (pin 3): a resistor to ground programs switching frequency. fb (pin 4): error amplifier inverting input. comp (pin 5): error amplifier output. allows various compensation networks for nonisolated applications. sync (pin 6): allows synchronization of internal oscillator to an external clock. f sync equal to f osc allowed. ss1 (pin 7): capacitor controls soft-start/stop of switch - ing frequency and volt-second clamp. during soft-stop it also controls the comp pin. ivsec (pin 8): resistor programs out pin maximum duty cycle clamp (d vsec ). this clamp moves inversely proportional to system input voltage to provide a volt- second clamp. uvlo_v sec (pin 9): a resistor divider from system in- put allows switch maximum duty cycle to vary inversely proportional with system input. this volt-second clamp prevents transformer saturation for duty cycles above 5 0 %. resistor divider ratio programs undervoltage lockout (uvlo) threshold. a 5a pin current hysteresis allows programming of uvlo hysteresis. pin below 0.4v reduces v in currents to microamps. ovlo (pin 10): a resistor divider from system input programs overvoltage lockout (ovlo) threshold. fixed hysteresis included. t ao (pin 11): a resistor programs nonoverlap timing between aout rise and out rise control signals. t as (pin 12): resistors at t ao and t as define delay between sout fall and out rise (= t ao C t as ). t os (pin 13): resistor programs delay between out fall and sout rise. t blnk (pin 14): resistor programs extended blanking of i sensep and oc signals during mosfet turn-on. ss2 (pin 17): capacitor controls soft-start of comp pin. alternatively can connect to opto to communicate start of switching to secondary side. if unused, leave the pin open. gnd (pin 18): analog signal ground. electrical connection exists inside the ic to the exposed pad (pin 39). pgnd (pins 19, 38, 39): the power grounds for the ic. the package has an exposed pad (pin 39) underneath the ic which is the best path for heat out of the package. pin 39 should be soldered to a continuous copper ground plane under the device to reduce die temperature and increase the power capability of the lt3753. i sensen (pin 20): negative input for the current sense comparator. kelvin connect to the sense resistor in the source of the power mosfet. i sensep (pin 21): positive input for the current sense comparator. kelvin connect to the sense resistor in the source of the power mosfet. a resistor in series with i sensep programs slope compensation. oc (pin 22): an accurate 96mv threshold, independent of duty cycle, for detection of primary side mosfet over - current and trigger of hiccup mode. connect directly to sense resistor in the source of the primar y side mosfet. missing pins 23, 25, 27, 29, 31, 33, 35: pins removed for high voltage spacings and improved reliability. out (pin 24): drives the gate of an n-channel mosfet between 0v and intv cc . active pull-off exists in shutdown. intv cc (pin 26): a linear regulator supply generated from v in . supplies 10v for aout, sout and out gate drivers. intv cc must be bypassed with a 4.7f capacitor to power ground. can be externally driven by the housekeeping supply to remove power from within the ic. v in (pin 28): input supply pin. bypass with 1f to ground. sout (pin 30): sync signal for secondary side synchro - nous rectifier controller. aout (pin 32): control signal for external active clamp switch. test2 (pin 36): connect to gnd. lt3753 3753f
11 for more information www.linear.com/lt3753 b lock diagra m + ? 1.25v + ? + ? + ? + ? 1.25v (+) 1.215v (?) en_ss1 uvlo_v sec out 0.4v 5a ss1 > 1.25v hard stop 0.9ma 7.75v(+) 7.42v(?) v in soft stop ss1 < 150mv 20a (1 shot) uvlo_v sec 9 v in ovlo 10 ivsec 8 sync 100k 6 rt 3 ss2 17 ss1 fb 7 4 comp 5 t ao 11 t as 12 t os 13 t blnk gnd (+ exposed pad pin 39) (+ exposed pad pin 39) 14 18 pgnd (19, 38) + ? + ? 1.25v ref + ? 0.4a 0.4a 2a 1.25v osc fold back islp 1.25v 150mv hard stop soft start ss2 1.25v ss1 en_ss1 (0220)mv soft stop ss1 > 2.2v v sec clamp timing logic s r q s q ss1 < 1.25v t j > 170c intv cc_ov intv cc_uv r + ? + ? + ? + ? 28 intv cc 26 aout off on 96mv off fg cg on active clamp control synchronous control main switch 32 sout 30 out 24 oc 22 i sensep 21 i sensen 3753 bd 20 ea blank islp hiccup control lt3753 3753f
12 for more information www.linear.com/lt3753 ti m ing diagra m s figure 1. timing diagram figure 2. timing reference circuit t oa t ao t so t as t os 0v aout out swp sout cg fg fsw csw t (1/f osc ) t ao programmed by r tao , t as programmed by r tas t os programmed by r tos , t oa = 0.9 ? t ao , t so = t ao ? t as 0v 0v 0v 0v 0v v out /(1 ? duty cycle) v in /(1 ? duty cycle) 0v 0v 3753 f01 v in t ao t as aout m1 m4 fg cg sync m3 swp ltxxxx csw fsw gnd sout ? ? ? ? m2 ?v in v in ?v out 3753 f02 v out lt3753 out t os lt3753 3753f
13 for more information www.linear.com/lt3753 ti m ing diagra m s figure 3. start-up and shutdown timing diagram system input (min) +v hyst 1.25v 10v(reg) 2.6v 2.6v 2.6v 7v uvlo(+) 0v 0v 0v 0v 0v 0v 0hz 150mv 1.25v completed soft-stop shutdown: 0.6v < uvlo_v sec < 1.25v and ss1 < 150mv ss1 soft starts f osc and dv sec ss2 soft starts comp ss1 soft stops f osc , dv sec and comp system input (min) system input (v in pin) uvlo_v sec (resistor divider from system input) ss1 comp ss2 f osc (switching frequency) intv cc trigger soft stop comp switching threshold 1.25v full-scale f osc 3753 f03 switching full-scale f osc /4 lt3753 3753f
14 for more information www.linear.com/lt3753 o pera t ion introduction the lt3753 is a primary side, current mode, pwm control - ler optimized for use in a synchronous forward converter with active clamp reset. the l t3753 allows v in pin opera - tion between 8.5v and 100v. the lt3753 based forward converter is targeted for power levels up to 400w and is not intended for batter y charger applications. for higher power levels the converter outputs can be stacked in series. connecting uvlo_v sec pins, ovlo pins, ss1 pins and ss2 pins together allows blocks to react simultaneously to all fault modes and conditions. the ic contains an accurate programmable volt-second clamp. when set above the natural duty cycle of the con - verter, it provides a duty cycle guardrail to limit primary switch reset voltage and prevent transformer saturation during load transients. the accuracy and excellent line regulation of the volt-second clamp provides v out regu- lation for open-loop conditions such as no opto-coupler, reference or error amplifier on the secondar y side. for applications not requiring isolation but requiring high step-down ratios, each ic contains a voltage error ampli - fier to allow a very simple nonisolated, fully regulated synchronous for ward converter . a range of protection features include programmable overcurrent (oc) hiccup mode, programmable system input undervoltage lockout (uvlo), programmable system input overvoltage lockout (ovlo) and built-in thermal shutdown. programmable slope compensation and switching frequency allow the use of a wide range of output inductor values and transformer sizes. part start-up lt3753 start-up is best described by referring to the block diagram and to the start-up waveforms in figure?3. for part start-up, system input voltage must be high enough to drive the uvlo_v sec pin above 1.25v and the v in pin must be greater than 8.5v. an internal linear regulator is activated and provides a 10v intv cc supply for all gate drivers. the ss1 pin of the forward controller is allowed to start charging when intv cc reaches its 7v uvlo(+) thershold. when ss1 reaches 1.25v, the ss2 pin begins to charge, controlling comp pin rise and the soft-start of output inductor peak current. the ss1 pin independently soft starts switching frequency and a volt-second clamp from 22% of their full-scale programmed values. if secondary side control already exists for soft starting the converter output voltage then the ss2 pin can still be used to control initial inductor peak current rise. simply programming the primary side ss2 soft-start faster than the secondary side allows the secondary side to take over. if ss2 is not needed for soft-start control, its pull-down strength and voltage rating also allow it to drive the input of an opto-coupler connected to intv cc . this allows the option of communicating to the secondary side that switching has begun. lt3753 3753f
15 for more information www.linear.com/lt3753 figure 4. programming undervoltage lockout (uvlo) a pplica t ions i n f or m a t ion programming system input undervoltage lockout (uvlo) threshold and hysteresis the lt3753 has an accurate 1.25v shutdown threshold at the uvlo_v sec pin. this threshold can be used in conjunction with an external resistor divider to define the falling undervoltage lockout threshold (uvlo(C)) for the converters system input voltage (v s ) (figure 4). a pin hysteresis current of 5a allows programming of the uvlo(+) threshold. v s (uvlo(C)) [begin soft-stop then shut down] = 1.25 1+ r1 r2+r3 ? ? ? ? ? ? ? ? ? ? ? ? v s (uvlo(+)) [begin soft-start] = v s (uvlo(C)) + (5a ? r1) it is important to note that the part enters soft-stop when the uvlo_v sec pin falls back below 1.25v. during soft-stop the converter continues to switch as it folds back switching frequency, volt-second clamp and comp pin voltage. see soft-stop in the applications information section. when the ss2 pin is finally discharged below its 150mv reset threshold the forward converter is shut down. soft-stop shutdown soft-stop shutdown (similar to system undervoltage) can be commanded by an external control signal. a mosfet with a diode (or diodes) in series with the drain should be used to pull down the uvlo_v sec pin below 1.25v but not below the micropower shutdown threshold of 0.6v(max). typical v in quiescent current after soft-stop is 165a. micropower shutdown if a micropower shutdown is required using an external control signal, an open-drain transistor can be directly connected to the uvlo_v sec pin. the lt3753 has a micropower shutdown threshold of typically 0.4v at the uvlo_v sec pin. v in quiescent current in micropower shutdown is 20a. programming system input overvoltage lockout (ovlo) threshold the lt3753 has an accurate 1.25v overvoltage shutdown threshold at the ovlo pin. this threshold can be used in conjunction with an external resistor divider to define the rising overvoltage lockout threshold (ovlo(+)) for the converters system input voltage (v s ) (figure 5). when ovlo(+) is reached, the part stops switching immediately and a hard stop discharges the ss1 and ss2 pins. the falling threshold ovlo(C) is fixed internally at 1.205v and allows the part to restart in soft-start mode. a single resis - tor divider can be used from system input supply (v s ) to define both the undervoltage and overvoltage thresholds for the system. minimum value for r3 is 1k. if ovlo is unused, place a 10k resistor from ovlo pin to ground. v s ovlo(+) [stop switching; hard stop] = 1.25 1+ r1+r2 r3 ? ? ? ? ? ? ? ? ? ? ? ? v s ovlo(C) [begin soft-start] = v s ovlo + ( ) ? 1.215 1.25 1.250v 3753 f04 r1 r2 to ovlo pin r3 system input (v s ) uvlo_v sec lt3753 5a ? + lt3753 3753f
16 for more information www.linear.com/lt3753 a pplica t ions i n f or m a t ion figure 5. programming overvoltage lockout (ovlo) programming switching frequency the switching frequency for the lt3753 is programmed using a resistor, r t , connected from analog ground (pin 18) to the rt pin. table 1 shows typical f osc vs r t resistor values. the value for r t is given by: r t = 8.39 ? x ? (1 + y) where, x = (10 9 /f osc ) C 365 y = (300khz C f osc )/10 7 (f osc < 300khz) y = (f osc C 300khz)/10 7 (f osc > 300khz) example: for f osc = 200khz, r t = 8.39 ? 4635 ? (1 + 0.01) = 39.28k (choose 39.2k) the lt3753 includes frequency foldback at start-up (see figure 3). in order to make sure that a sync input does not override frequency foldback during start-up, the sync function is ignored until ss1 pin reaches 2.2v. table 1. r t vs switching frequency (f osc ) switching frequency (khz) r t (k) 100 82.5 150 53.6 200 39.2 250 30.9 300 24.9 350 21 400 18.2 450 15.8 500 choose 13.7 synchronizing to an external clock the lt3753 internal oscillator can be synchronized to an external clock at the sync pin. sync pin high level should exceed 1.8v for at least 100ns and sync pin low level should fall below 0.6v for at least 100ns. the sync pin frequency should be set equal to or higher than the typical frequency programmed by the rt pin. an f sync /f osc ratio of x (1.0 < x < 1.25) will reduce the externally programmed slope compensation by a factor of 1.2x. if required, the external resistor r islp can be reprogrammed higher by a factor of 1.2x. (see current sensing and programmable slope compensation). the part injection locks the internal oscillator to every ris - ing edge of the sync pin. if the sync input is removed at any time during normal operation the part will simply change switching frequency back to the oscillator frequency programmed by the r t resistor. this injection lock method avoids the possible issues from a pll method which can potentially cause a large drop in frequency if sync input is removed. during soft-start the sync input is ignored until ss1 ex - ceeds 2.2v. during soft-stop the sync input is completely ignored. if the sync input is to be used, recall that the programmable duty cycle clamp d vsec is dependent on the switching frequency of the part (see section programming duty cycle clamp). r ivsec should be reprogrammed by 1/x for an f sync /f osc ratio of x. intv cc regulator bypassing and operation the intv cc pin is the output of an internal linear regulator driven from v in and provides a 10v supply for onboard gate drivers aout, sout and out. intv cc should be bypassed with a 4.7f low esr, x7r or x5r ceramic capacitor to power ground to ensure stability and to provide enough charge for the gate drivers. the intv cc regulator has a minimum 19ma output cur - rent limit. this current limit should be considered when c ho osing the switching frequency and capacitance loading on each gate driver. average current load on the intv cc pin for a single gate driver driving an external mosfet is given as : i intvcc = f osc ? q g 1.250v(+) 1.215v(?) 3753 f05 r1 r2 ovlo to uvlo_v sec pin r3 system input (v s ) lt3753 ovlo ? + lt3753 3753f
17 for more information www.linear.com/lt3753 a pplica t ions i n f or m a t ion where: f osc = controller switching frequency q g = gate charge (v gs = intv cc ) while the intv cc 19ma output current limit is sufficient for lt3753 applications, efficiency and internal power dissipation should also be considered. intv cc can be externally overdriven by an auxiliary supply (see gener - ating auxiliary supplies in the applications information section) to improve efficiency , remove power dissipation from within the ic and provide more than 19ma output current capability . any overdrive level should exceed the regulated intv cc level but not exceed 16v. in the case of a short-circuit fault from intv cc to ground, the ic reduces the intv cc output current limit to typically 13ma. the intv cc regulator has an undervoltage lockout rising threshold, uvlo(+), which prevents gate driver switching until intv cc reaches 7v and maintains switch - ing until intv cc falls below a uvlo(C) threshold of 6.8v. for v in levels close to or below the intv cc regulated level, the intv cc linear regulator may enter dropout. the result - ing lower intv cc level will still allow gate driver switching as long as intv cc remains above intv cc uvlo(C) levels. see the typical performance characteristics section for intv cc performance vs v in and load current. adaptive leading edge blanking plus programmable extended blanking the lt3753 provides a 2a gate driver at the out pin to control an external n-channel mosfet for main power delivery in the forward converter (figure 7). during gate rise time and sometime thereafter, noise can be generated in the current sensing resistor connected to the source of the mosfet. this noise can potentially cause a false trip of sensing comparators resulting in early switch turn off and in some cases re-soft-start of the system. to prevent this, lt3753 provides adaptive leading edge blanking of both oc and i sensep signals to allow a wide range of mosfet q g ratings. in addition, a resistor r tblnk connected from t blnk pin to analog ground (pin?18) programs an extended blanking duration (figure 6). adaptive leading edge blanking occurs from the start of out rise and completes when out reaches within 1v of its maximum level. an extended blanking then occurs which is programmable using the r tblnk resistor given by: t blnk = 50ns + 2.2ns k ? r tblnk ? ? ? ? ? ? , 7.32k < r tblnk < 249k adaptive leading edge blanking minimizes the value re - quired for r tblnk . increasing r tblnk further than required increases m1 minimum on time (figure 7). in addition, the critical volt-second clamp (d vsec ) is not blanked. therefore, if d vsec decreases far enough (in soft start foldback and at maximum input voltage) m1 may turn off before blanking has completed. since oc and i sensep signals are only seen when m1 is on (and after blanking has completed), r tblnk value should be limited by: (2.2ns/k)r tblnk < t vsec(min) C t adaptive C 50ns (adaptive) leading edge blanking (programmable) extended blanking 7.32k r tblnk 249k t blnk = 50ns + (2.2ns ? r tblnk ) current sense delay 220ns k 3753 f06 out figure 6. adaptive leading edge blanking plus programmable extended blanking v in v in intv cc v out m1 r sense 3753 f07 r islp ? ? ltc3753 intv cc comp out oc i sensep from regulation loop i sensen gnd figure 7. current sensing and programmable slope compensation lt3753 3753f
18 for more information www.linear.com/lt3753 a pplica t ions i n f or m a t ion where, t vsec(min) = 10 9 (d vsec (max) /(fold.fosc)) ? (input (min) /input (max) ) fold = f osc and d vsec foldback ratio (for out pin) t adaptive = out pin rise time to intv cc C 1v example: for figure 22 circuit, d vsec(max) = 0.77, input (min)/(max) = 17.4v/74v, fold = 4, t adaptive = 23ns and f osc = 240khz, t vsec(min) = 10 9 (0.77/(4 ? 2.4 ? 10 5 )) ? 17.4/74 = 188ns (2.2ns/1k)r tblnk < 188 C 23 C 50 r tblnk < 52.5k (actual circuit uses 34k) current sensing and programmable slope compensation the lt3753 commands cycle-by-cycle peak current in the external switch and primary winding of the forward trans - former by sensing voltage across a resistor connected in the sour ce of the external n-channel mosfet (figure 7). the sense voltage across r sense is compared to a sense threshold at the i sensep pin, controlled by comp pin level. two sense inputs, i sensep and i sensen , are provided to allow a kelvin connection to r sense . for operation in con - tinuous mode and above 50% duty cycle, required slope compensation can be programmed by adding a resistor , r islp , in series with the i sensep pin. a ramped current always flows out of the i sense pin. the current starts from 2a at 0% duty cycle and linearly ramps to 33a at 80% duty cycle. a good starting value for r islp is 1.5k which gives a 41mv total drop in current comparator threshold at 65% duty cycle. the comp pin commands an i sensep threshold between 0mv and 220mv. the 220mv allows a large slope com - pensation voltage drop to exist in r islp without effecting the programming of r sense to set maximum operational currents in m1. an f sync /f osc ratio of x (1.0 < x < 1.25) will reduce the externally programmed slope compensa - tion by a factor of 1.2x. if required, the external resistor r islp can be reprogrammed higher by a factor of 1.2x. overcurrent: hiccup mode the lt3753 uses a precise 96mv sense threshold at the oc pin to detect excessive peak switch current (figure 7). during an overload condition switching stops imme - diately and the ss1/ss2 pins are rapidly discharged. the absence of switching reduces the sense voltage at the oc pin, allowing ss1/ss2 pins to recharge and eventually attempt switching again. the part exists in this hiccup mode as long as the overcurrent condition exists. this protects the converter and reduces power dissipation in the components (see hard stop in the applications information section). the 96mv peak switch current threshold is independent of the voltage drop in r islp used for slope compensation. output dc load current to trigger hiccup mode: = i load(overcurrent) = n p n s ? 96mv r isense ? ? ? ? ? ? C 1/2 i ripple(p-p) ( ) where: n p = forward transformer primary turns n s = forward transformer secondary turns i ripple(p-p) = output inductor peak-to-peak ripple current r isense should be programmed to allow maximum dc load current for the application plus enough margin during load transients to avoid overcurrent hiccup mode. programming maximum duty cycle clamp: d vsec (volt-second clamp) unlike other converters which only provide a fixed maximum duty cycle clamp, the l t3753 provides an accurate programmable maximum duty cycle clamp (d vsec ) on the out pin which moves inversely with system input. d vsec provides a duty cycle guardrail to limit the volt-seconds-on product over the entire lt3753 3753f
19 for more information www.linear.com/lt3753 a pplica t ions i n f or m a t ion natural duty cycle range (figures 8 and 9). this limits the drain voltage required for complete transformer reset. a resistor r ivsec from the ivsec pin to analog ground (pin 18) programs d vsec . d vsec (out pin duty cycle clamp) = 0.725 ? r ivsec 51.1k ? f osc 300 ? 1.25 uvlo_v sec where: r ivsec = programming resistor at ivsec pin f osc = switching frequency (khz) uvlo_v sec = resistor divided system input voltage r ivsec can program any d vsec required at minimum system input. d vsec will then follow natural duty cycle as v in varies. maximum programmable d vsec is typi - cally 0.75 but may be further limited by the transformer design and voltage ratings of components connected to the drain of the primar y side power mosfet (swp). see voltage calculations in the lo side and hi side active clamp topologies sections. if system input voltage falls below it's uvlo threshold the part will enter soft-stop with continued switching. the l t3753 includes an intelligent circuit which prevents d vsec from continuing to rise as system input voltage falls (see soft-stop). without this, too large a d vsec would require extremely high reset voltages on the swp node to prop - erly reset the transformer. the uvlo_v sec pin maximum operational level is the lesser of v in C 2v or 12.5v. the lt3753 volt-second clamp architecture is superior to an external rc network connected from system input to trip an internal comparator threshold. the rc method suffers from external capacitor error, part-to-part mismatch between the rc time constant and the ics switching period, the error of the internal comparator threshold and the nonlinearity of charging at low input voltages. the lt3753 uses the r ivsec resistor to define the charge current for an internal timer capacitor to set an out pin maximum on-time, t on(vsec) . the voltage across r ivsec follows uvlo_v sec pin voltage (divided down from system input voltage). hence, r ivsec current varies linearly with input supply. the lt3753 also trims out internal timing capacitor and comparator threshold errors to optimize part-to-part matching between t on(vsec) and t. d vsec open loop control: no opto-coupler, error amplifier or reference the accuracy of the programmable volt-second clamp (d vsec ) safely controls v out if open loop conditions exist such as no opto-coupler, error amplifier or reference on the secondary side. d vsec controls the output of the converter by controlling duty cycle inversely proportional to system input. if d vsec duty cycle guardrail is programmed x% above natural duty cycle, v out will only increase by x% if a closed loop system breaks open. this volt-second clamp is operational over a 10:1 system input voltage range. see d vsec versus uvlo_v sec pin voltage in the typical performance characteristics section. r ivsec : open pin detection provides safety the lt3753 provides an open-detection safety feature for the r ivsec pin. if the r ivsec resistor goes open circuit the part immediately stops switching. this prevents the part from running without the volt-second clamp in place. t on_vsec t on out t d = t on /t 3753 f08 (programmed by r ivsec ) dv sec = t on_vsec /t dv sec = ?duty cycle guardrail? 3753 f09 r1 r2 uvlo_v sec to ovlo pin r3 r ivsec system input lt3753 ivsec rt r t figure 8. volt-second (d vsec ) clamp figure 9. programming d vsec lt3753 3753f
20 for more information www.linear.com/lt3753 a pplica t ions i n f or m a t ion transformer reset: active clamp technique the lt3753 includes a 0.4a gate driver at the aout pin to allow the use of an active clamp transformer reset technique (figures 10, 14). the active clamp method improves efficiency and reduces voltage stress on the main power switch, m1. by switching in the active clamp capacitor only when needed, the capacitor does not lose its charge during m1 on-time. by allowing the active clamp capacitor, c cl , to store the average voltage required to reset the transformer, the main power switch sees lower drain voltage. in addition, the active clamp drain waveform on m1 (figure 11) allows a self-driven architecture, whereby the drains of m3 and m4 drive the gates of m4 and m3 respectively , removing the need for a secondar y-side synchronous mosfet driver (figure 21). in a self-driven architecture, the reset voltage level on m1, v out level and duty cycle range (governed by system input range) must be considered to ensure the maximum v gs rating of synchronous mosfets m3, m4 are not exceeded. an imbalance of volt-seconds will cause magnetizing cur - rent to walk upwards or downwards until the active clamp capacitor is charged to the optimal voltage for proper transformer reset. the voltage rating of the capacitor will depend on whether the active clamp capacitor is actively switched to ground (figure 10) or actively switched to system input (figure 14). in an active clamp reset topol - ogy, volt-second balance requires: v in ? d = (swp C v in ) ? (1 C d) where: v in = transformer input supply d = (v out /v in ) ? n = switch m1 duty cycle v out = output voltage (including the voltage drop contribution of m4 catch diode during m1 off) n = transformer turns ratio = n p /n s swp = m1 drain voltage lo side active clamp topology (lt3753) the steady-state active clamp capacitor voltage, v ccl , required to reset the transformer in a lo side active clamp topology (figure 10) can be approximated as the drain-to- source voltage (v ds ) of switch m1, given by: v ccl (lo side): (a) steady state: v ccl = swp = v ds = 1 1C d ? ? ? ? ? ? ? v in = v in 2 v in C v out ? n ( ) ( ) (b) transient: during load transients, duty cycle and hence v ccl may increase. replace d with d vsec in the equation above to calculate transient v ccl values. see the previous section programming duty cycle clampCd vsec . the d vsec guard - rail can be programmed as close as 5% higher than d but may require a larger margin to improve transient response. figure 10. lo side active clamp topology c cl l leak l leak l mag fsw csw ? ? v d d1r1 c1 m2 m4 m3 m1 swp out v in ?v in v out ?v out aout lt3753 fg ltxxxx cg 3753 f10 lt3753 3753f
21 for more information www.linear.com/lt3753 a pplica t ions i n f or m a t ion as shown in figure 12, the maximum steady-state value for v ccl may occur at minimum or maximum input volt - age. hence v ccl should be calculated at both input voltage levels and the largest of the two calculations used. m1 drain should be rated for a voltage greater than the above steady-state v ds calculation due to tolerances in duty cycle, load transients, voltage ripple on c cl and leakage inductance spikes. c cl should be rated higher due to the effect of voltage coefficient on capacitance value. a typical choice for c cl is a good quality x7r capacitor. m2 should have a v ds rating greater than v ccl since the bottom plate of c cl is Cv ccl during m1 on and m2 off. for high input voltage applications, the limited v ds rating of available p-channel mosfets might require changing from a lo side to hi side active clamp topology. for the lo side active clamp topology in steady state, during m1 on time, magnetizing current (i mag ) increases from a negative value to a positive value (figure 11). when m1 turns off, magnetizing current charges swp until it reaches v ccl plus the voltage drop of the m2 body diode. at this figure 12. lo side v ccl vs duty cycle (normalized to 50% duty cycle) figure 11. active clamp reset: magnetizing current and m1 drain voltage 20s/div i mag 1a/div swp 50v/div 3753 f11 duty cycle (%) 20 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 50 70 3753 f12 30 40 60 80 active clamp capacitor voltage normalized to 50% duty cycle lo side active clamp topology figure 13. hi side v ccl vs duty cycle (normalized to 50% duty cycle) figure 14. hi side active clamp topology (using lt3752-1) duty cycle (%) 20 active clamp capacitor voltage normalized to 50% duty cycle 1.5 3753 f13 1.0 0.5 40 60 30 50 70 2.0 2.5 1.3 0.8 1.8 2.3 80 hi side active clamp topology c cl l leak l leak swp l mag fsw csw ? ? ? ? v d d1 ?v in c2 t4 c1 m2 m4 m1 m3 r1 out v in ?v in v out ?v out aout lt3752-1 fg ltxxxx cg 3753 f14 lt3753 3753f
22 for more information www.linear.com/lt3753 a pplica t ions i n f or m a t ion moment the active clamp capacitor is passively switched in to ground (due to the forward conduction of m2 body diode) and the drain voltage increases at a slower rate due to the loading of c cl . swp above v in causes i mag to reduce from a positive value towards zero (dv swp /dt = 0). as i mag becomes negative it begins to discharge the swp node. switching in m2 before i mag reverses, actively connects the bottom plate of c cl to ground and allows swp to be discharged slowly. the resulting swp waveform during m1 off-time appears as a square wave with a superimposed sinusoidal peak representing ripple voltage on c cl . the switch m2 experiences near zero voltage switching (zvs) since only the body diode voltage drop appears across it at switch turn on. hi side active clamp topology (lt3752-1) for high input voltage applications the v ds rating of avail - able p-channel mosfets might not be high enough to be used as the active clamp switch in the lo side active clamp topology (figure 10). an n-channel approach using the hi side active clamp topology (figure 14) should be used. (the l t3752-1 is ideal for the hi side active clamp topology). this topology requires a gate drive transformer or a simple gate drive opto-coupler to drive the n-channel mosfet (m2) for switching in the active clamp capacitor from swp to v in . the m1 drain voltage calculation is the same as in the lo side active clamp case and m1 should be rated in a similar manner. the voltage across the clamp capacitor in the hi side architecture, however, is lower by v in since it is referenced to v in . the steady-state active clamp capacitor voltage v ccl to reset the transformer in a hi side active clamp topology can be approximated by: v ccl (hi side): (a) steady state: v ccl = v reset = v ds C v in = d 1C d ? ? ? ? ? ? ? v in = v in ? v out ? n v in C v out ? n ( ) (b) transient: during load transients, duty cycle and hence v ccl may increase. replace d with d vsec in the equation above to calculate transient v ccl values. d vsec guardrail can be programmed as close as 6% higher than d but may require a larger margin to improve transient response. see the previous section programming duty cycle clampCd vsec . c cl should be rated for a voltage higher than the above steady-state calculation due to tolerances in duty cycle, load transients, voltage ripple on c cl and the effect of voltage coefficient on capacitance value. a typical choice for c cl is a good quality (x7r) capacitor. when using a gate drive transformer to provide control of the active clamp switch (m2), the external components c1, c2, r1, d1 and t4 are required. t4 size will increase for lower programmed switching frequencies due to a minimum volt-second requirement. alternatively, a simple gate driver opto-coupler can be used as a switch to control m2, for a smaller solution size. active clamp capacitor value and voltage ripple the active clamp capacitor value should be chosen based on the amount of voltage ripple which can be tolerated by components attached to swp. lower c cl values will create larger voltage ripple (increased drain voltage for the primary side power mosfet) but will require less swing in magnetizing current to move the active clamp capacitor during duty cycle changes. choosing too high a value for the active clamp capacitor (beyond what is needed to keep ripple voltage to an acceptable level) will require unneces - sary additional flux swing during transient conditions. for systems with flux swing detection, too high a value for the active clamp capacitor will trigger the detection system early and degrade transient response. another factor to consider is the resonance between c cl and the magnetizing inductance (l mag ) of the main transformer. an rc snubber (r s , c s ) in parallel with c cl will dampen lt3753 3753f
23 for more information www.linear.com/lt3753 a pplica t ions i n f or m a t ion the sinusoidal ringing and limit the peak voltages at the primary side mosfet drain during input/load transients. check circuit performance to determine if the snubber is required. component values can be approximated as: c cl (active clamp capacitance) = 10 l mag ? (1C d min ) 2 ? ? f osc ? ? ? ? ? ? 2 where, d min = (v out /v in(max) ) ? n p /n s and (if needed), c s (snubber capacitance) = 6 ? c cl r s (snubber resistance) = (1/(1-d max )) ? (l mag /c cl ) where, d max = ( v out /v in(min) ) ? n p /n s check the voltage ripple on swp during steady-state operation. c cl voltage ripple can be estimated as: v ccl(ripple) = v ccl ? (1-d) 2 /(8 ? c cl ? l mag ? f osc 2 ) where, d = (v out /v in ) ? (n p /n s ) v ccl = v in /(1-d) (lo side active clamp topology) v ccl = d ? v in /(1-d) (hi side active clamp topology) example : for v in = 36v, v out = 12v, n p /n s = 2, v ccl = 108v (lo side active clamp topology), c cl = 22nf, l mag = 100h, f osc = 250khz, v ccl(ripple) = 108(0.33) 2 /(8(22 ? 10 C9 )(10 C4 )(2.5 ? 10 4 ) 2 ) = 10.7v the transformer is typically chosen to operate at a maximum flux density that is low enough to avoid excessive core losses. this also allows enough headroom during input and load transients to move the active clamp capacitor at a fast enough rate to keep up with duty cycle changes. active clamp mosfet selection the selection of active clamp mosfet is determined by the maximum levels expected for the drain voltage and drain current. the active clamp switch (m2) in a either a lo side or hi side active clamp topology has the same bvdss requirements as the main n-channel power mosfet. the current requirements are divided into two categories : (a) drain current this is typically less than the main n-channel power mosfet because the active clamp mosfet sees only magnetizing current, estimated as : peak i mag (steady state) = (1/2) ? (n p /n s ) ? (v out / l mag ) ? (1/f osc ) where, l mag = main transformers magnetizing inductance example (lt3752) : for v out =12v, n p /n s = 2, f osc = 250khz and l mag = 100h, peak i mag = 0.48a. this value should be doubled for safety margin due to variations in l mag , f osc and transient conditions. (b) body diode current the body diode will see reflected output current as a pulse every time the main n-channel power mosfet turns off. this is due to residual energy stored in the transformer's leakage inductance. the body diode of the active clamp mosfet should be rated to withstand a forward pulsed current of: i d(max) = (n s /n p ) (i out(max) + (i l(ripple)(p-p) /2)) where, i l(ripple)(p-p) = output inductor ripple current = (v out / (l out ? f osc )) ? (1C(v out /v in )(n p /n s )) i out(max) = maximum output load current lt3753 3753f
24 for more information www.linear.com/lt3753 a pplica t ions i n f or m a t ion programming active clamp switch timing: aout to out (t ao ) and out to aout (t oa ) delays the timings t ao and t oa represent the delays between aout and out edges (figures 1 and 2) and are programmed by a single resistor, r tao , connected from analog ground (pin 18) to the t ao pin. once t ao is programmed for the reasons given below, t oa will be automatically generated. front-end timing t ao (m2 off, m1 on) = aout(edge)-to-out(rising) = 50ns + 3.8ns ? r tao 1k ? ? ? ? ? ? ,14.7 < r tao < 125k in order to minimize turn-on transition loss in m1 the drain of m1 should be as low as possible before m1 turns on. to achieve this, aout should turn m2 off a delay of t ao before out turns m1 on. this allows the main transformers magnetizing current to discharge m1 drain voltage quickly towards v in before m1 turns on. as swp falls below v in , however, the rectifying diodes on the secondary side are typically active and clamp the swp node close to v in . if enough leakage inductance exists, however, the clamping action on swp by the secondary side will be delayedpotentially allowing the drain of m1 to be fully discharged to ground just before m1 turns on. even with this delay due to the leakage inductance, l mag needs to be low enough to allow i mag to be negative enough to slew swp down to ground before m1 turns on. if achievable, m1 will experience zero voltage switching (zvs) for highest efficiency. as will be seen in a later sec - tion entitled primary-side power mosfet selection, m1 transition loss is a significant contributor to m1 losses. back-end timing t oa (m1 off, m2 on) is automatically generated = out(falling)-to-aout(edge) = 0.9 ? t ao t oa should be checked to ensure m2 is not turned on until m1 and m3 are turned off. programming synchronous rectifier timing: sout to out (t so ) and out to sout (t os ) delays the lt3753 includes a 0.4a gate driver at the sout pin to send a control signal via a pulse transformer to the secondary side of the forward converter for synchronous rectification (see figures 1 and 2). for the highest efficiency, m4 should be turned on whenever m1 is turned off. this suggests that sout should be a non-overlapping signal with out with very small non-overlap times. inherent tim - ing delays, however, which can vary from application to application, can exist between out to csw and between sout to cg. possible shoot-through can occur if both m1 and m4 are on at the same time, resulting in transformer and/or switch damage. front-end timing: t so (m4 off, m1 on) = sout(falling)-to-out(rising) delay = t so = t ao C t as = 3.8ns ? (r tas C r tao ) where: t as = 50ns + (3.8ns ? r tas /1k) , 14.7k < r tas < 125k, t ao = 50ns + (3.8ns ? r tao /1k), 14.7k < r tao < 125k, t so is defined by resistors r tas and r tao connected from analog ground (pin 18) to their respective pins t as and t ao . each of these resistor defines a delay referenced to the aout edge at the start of each cycle. r tao was already programmed based on requirements defined in the previous section programming aout to out delay. r tas is then programmed as a delay from aout to sout to fulfill the equation above for t so . by choosing r tas less than or greater than r tao , the delay between sout falling and out rising can be programmed as positive or nega - tive. while a positive delay can always be programmed for t so , the ability to program a negative delay allows for improved efficiency if out(rising)-to-csw(rising) delay is larger than sout(falling)-to-cg(rising) delay. back-end timing: t os (m1 off, m4 on) = out (falling)-to-sout (rising) delay = t os = 35ns + (2.2ns ? r tos /1k), 7.32k < r tos < 249k lt3753 3753f
25 for more information www.linear.com/lt3753 a pplica t ions i n f or m a t ion the timing resistor, r tos , defines the out (falling)-to-sout (rising) delay. this pin allows programming of a positive delay, for applications which might have a large inherent delay from out fall to sw2 fall. soft-start (ss1, ss2) the lt3753 uses ss1 and ss2 pins for soft starting various parameters (figures 3 and 15). ss1 soft starts internal oscillator frequency and d vsec (maximum duty cycle clamp). ss2 soft starts comp pin voltage to control output inductor peak current. using separate ss1 and ss2 pins allows the soft-start ramp of oscillator frequency and d vsec to be independent of comp pin soft-start. typically ss1 capacitor (c ss1 ) is chosen as 0.47f and ss2 capacitor (c ss2 ) is chosen as 0.1f. soft-start charge currents are 11.5a for ss1 and 21a for ss2. ss1 is allowed to start charging (soft-start) if all of the following conditions exist (typical values) : (1) uvlo_v sec > 1.25v: system input not in uvlo (2) ovlo < 1.215v: system input not in ovlo (3) oc < 96mv: no over current condition (4) 7v < intv cc < 16v: intv cc valid (5) t j < 165c: junction temperature valid (6) v in > 7.75v: v in pin valid ss1 = 0v to 1.25v (no switching). this is the ss1 range for no switching for the forward converter. ss2 = 0v. ss1 > 1.25v allows ss2 to begin charging from 0v. ss1 = 1.25v to 2.45v (soft-start f osc , d vsec ). this is the ss1 range for soft-starting f osc and d vsec folded back from 22% to 100% of their programmed levels. fold back of f osc and d vsec reduces effective minimum duty cycle for the primary side mosfet. this allows inductor current to be controlled at low output voltages during start-up. ss1 ramp rate is chosen slow enough to ensure f osc and d vsec foldback lasts long enough for the converter to take control of inductor current at low output voltages. in ad - dition, slower ss1 ramp rate increases the non-switching period during an output short to ground fault (over current hiccup mode) to reduce average power dissipation (see hard-stop). ss2 = 0v to 1.6v (soft-start comp pin). this is the ss2 range for soft-starting comp pin from approximately 1v to 2.6v. ss2 ramp rate is chosen fast enough to allow a (slower) soft-start control of comp pin from a secondar y side opto-coupler controller. ss1 soft-start non-switching period (0v to 1.25v) = 1.25v ? c ss1 /11.5a ss1 soft-start f osc , d vsec period (1.25v to 2.45v) = 1.2v ? c ss1 /11.5a ss2 soft-start comp period (0v to 1.6v) = 1.6v ? c ss2 /21a soft-stop (ss1) the lt3753 gradually discharges the ss1 pin (soft-stop) when a system input uvlo occurs or when an external soft-stop shutdown command occurs (0.4v < uvlo_v sec < 1.25v). during ss1 soft-stop the converter continues to switch, folding back f osc , d vsec and comp pin voltage (figures 3 and 15). soft-stop discharge current is 10.5a for ss1. soft-stop provides: (1 ) act ive control of the secondary winding during output discharge for clean shutdown in self-driven applica- tions. (2) controlled discharge of the active clamp capacitor to minimize magnetizing current swing during restart. ss1: 2.45v to 1.25v (soft-stop f osc , d vsec , comp). this is the ss1 range for soft-stop folding back of: (1) f osc and d vsec from 100% to 22% of their programmed levels. (2 ) comp pin (100% to 0% of commanded peak current). ss1 soft-stop f osc , d vsec , comp period (2.45v to 1.25v) = 1.2v ? c ss1 /10.5a lt3753 3753f
26 for more information www.linear.com/lt3753 a pplica t ions i n f or m a t ion ss1 < 1.25v. forward converter stops switching and ss2 pin is discharged to 0v using 2.8ma. ss1 = 1.25v to 0v: when ss1 falls below 0.15v the internal ss1 latch is reset. if all faults are removed, ss1 begins charging again. if faults still remain, ss1 discharges to 0v. ss1 soft-stop non-switching period (1.25v to 0v) = 1.25v ? c ss1 /10.5a d vsec rises as system input voltage falls in order to provide a maximum duty cycle guardrail (volt-second clamp). when system input falls below it's uvlo threshold, however, this triggers a soft-stop with the converter continuing to switch. it is important that d vsec no longer increases even though system input voltage may still be falling. the lt3753 achieves an upper clamp on d vsec by clamping the minimum level for the i vsec pin to 1.25v. as ss1 pin discharges during soft-stop it folds back d vsec . as d vsec falls below the natural duty cycle of the converter, the converter loop follows d vsec . if the system input voltage rises (i vsec pin rises) during soft-stop the volt-second clamp circuit further reduces d vsec . the i.c. chooses the lowest d vsec commanded by either the i vsec pin or the ss1 soft-stop function. hard-stop (ss1, ss2) switching immediately stops and both ss1 and ss2 pins are rapidly discharged (figure 15. hard-stop) if any of the following faults occur (typical values): (1) uvlo_v sec < 0.4v: micropower shutdown (2) ovlo > 1.250v: system input ovlo (3) oc > 96mv: over current condition (4) intv cc < 6.8v(uvlo), > 16.5v (ovlo) (5) t j > 170c: thermal shutdown (6) v in < 7.42: v in pin uvlo figure 15. ss1, ss2 and comp pin voltages during faults, soft-start and soft-stop comp range 2.6v 2.6v 0v 0v 1.25v 0.15v 0.25v comp 1.25v switching threshold ss2 soft starts comp 0v 1v comp ss2 ss1 2.6v hard stop soft-start (when all conditions satisfied) (1) uvlo_v sec > 1.25v (2) ovlo < 1.215v (3) oc < 96mv (4) 7v < intv cc < 16v (5) t j < 165c (6) v in > 7.75v soft-stop (0.4v < uvlo_v sec < 1.25) (1) external soft-stop shutdown (2) system input uvlo hard stop (faults) (1) uvlo_v sec < 0.4v (2) ovlo > 1.25v (3) oc > 96mv (4) intv cc < 6.8v, > 16.5v (5) t j > 170c (6) v in < 7.42v 3753 f15 ss1 soft stops f osc , d vsec and comp ss1 soft starts f osc and d vsec ss1 latch reset threshold lt3753 3753f
27 for more information www.linear.com/lt3753 a pplica t ions i n f or m a t ion switching stops immediately for any of the faults listed above. when ss1 discharges below 0.15v it begins charg- ing again if all faults have been removed. for an over cur - rent fault triggered by oc > 96mv, the disable of switching will cause the oc pin voltage to fall back below 96mv. this will allow ss1 and ss2 to recharge and eventually attempt switching again. if the over current condition still exists, oc pin will exceed 96mv again and the discharge/ charge cycle of ss1 and ss2 will repeat in a hiccup mode. the non-switching dead time period during hiccup mode reduces the average power seen by the converter in an over current fault condition. the dead time is dominated by ss1 recharging from 0.15v to 1.25v. non-switching period in over current (hiccup mode): = 1.1v ? c ss1 /11.5a out, aout, sout pulse-skipping mode during load steps, initial soft-start, end of soft-stop or light load operation (if the forward converter is designed to operate in dcm), the loop may require pulse skipping on the out pin. this occurs when the comp pin falls below its switching threshold. if the comp pin falls below it's switching threshold while out is turned on, the lt3753 will immediately turn out off ; both aout and sout will complete their normal signal timings referenced from the out falling edge. if the comp pin remains below it's switching threshold at the start of the next switching cycle, the lt3753 will skip the next out pulse and therefore also skip aout and sout pulses. for aout control, this pre - vents the active clamp capacitor from being accidentally discharged during missing out pulses and/or causing reverse saturation of the transformer . for sout control, this prevents the secondar y side synchronous rectifier controller from incorrectly switching between forward fet and synchronous fet conduction. the lt3753 correctly re-establishes the required aout, sout control signals if the out signal is required for the next cycle. aout timeout during converter start-up in soft-start, the switching fre - quency and maximum duty cycle clamp d vsec are both folded back. while this correctly reduces the effective minimum on time of the out pin (to allow control of induc - tor current for very low output voltages during start-up), this means the aout pin on time duration can be large. in order to ensure the active clamp switch controlled by aout does not stay on too long, the lt3753 has an internal 15s timeout to turn off the aout signal. this prevents the active clamp capacitor from being connected across the transformer primary winding long enough to create reverse saturation. main transformer selection the selection of the main transformer will depend on the applications requirements : isolation voltage, power level, maximum volt-seconds, turns ratio, component size, power losses and switching frequency. transformer construction using the planar winding technol - ogy is typically chosen for minimizing leakage inductance and reducing component height. t ransformer core type is usually a ferrite material for high frequency applications. find a family of transformers that meet both the isolation and power level requirements of the application. the next step is to find a transformer within that family which is suitable for the application. the subsequent thought pro - cess for the transformer design will include : (1) secondary turns (n s ), core losses, temperature rise, flux density, switching frequency (2) primary turns (n p ), maximum duty cycle and reset voltages (3) copper losses the expression for secondary turns (n s ) is given by, n s = 10 8 v out /(f osc ? a c ? b m ) lt3753 3753f
28 for more information www.linear.com/lt3753 where, a c = cross-sectional area of the core in cm 2 b m = maximum ac flux density desired for flux density, choose a level which achieves an accept - able level of core loss/temperature rise at a given switching frequency . the transformer data sheet will provide cur ves of core loss versus flux density at various switching fre - quencies. the data sheet will also provide temperature rise versus core loss. while choosing a value for bm to avoid excessive core losses will usually allow enough headroom for flux swing during input / load transients, still make sure to stay well below the saturation flux density of the transformer core. if needed, increasing n s will reduce flux density. after calculating n s , the number of primary turns (n p ) can be calculated from, n p = n s ? d max v in(min) /v out where, v in(min) = minimum system input voltage d max = maximum switch duty cycle at v in(min) (typically chosen between 0.6 and 0.7) at minimum input voltage the converter will run at a maxi - mum duty cycle d max . a higher transformer turns ratio (n p /n s ) will create a higher d max but it will also require higher voltages at the drain of the primary side switch to reset the transformer (see previous sections lo side ac - tive clamp topology and hi side active clamp topology). d max values are typically chosen between 0.6 and 0.7. even for a given d max value, the loop must also provide protection against duty cycles that may excessively exceed d max during transients or faults. while most converters only provide a fixed duty cycle clamp, the lt3753 provides a programmable maximum duty cycle clamp d vsec that also moves inversely with input voltage. the resulting function is that of a programmable volt- second clamp. this allows the user to choose a transformer turns ratio for d max and then customize a maximum duty cycle clamp d vsec above d max for safety. d vsec then follows the natural duty cycle of the converter as a safety guardrail (see previous section programming duty cycle clamp). after deciding on the particular transformer and turns ratio, the copper losses can then be approximated by, p cu = d ? i(load) (max) 2 (r sec + (n s /n p ) 2 r pri ) where, d = switch duty cycle (choose nominal 0.5) i(load) (max) = maximum load current r pri = primary winding resistance r sec = secondary winding resistance if there is a large difference between the core losses and the copper losses then the number of secondary turns can be adjusted to achieve a more suitable balance. the number of primary turns should then be recalculated to maintain the desired turns ratio. generating auxiliary supplies in many isolated forward converter applications, an aux - iliary bias may be required for the primary-side circuitry and/or the secondary-side circuitry. this bias is required for various reasons: to limit voltages seen by an ic, to improve efficiency, to remove power dissipation from inside an ic and/or to power an ic before target output voltage regulation is achieved ((eg) during v out start-up). the best method for generating an auxiliary supply, that is available even for v out = 0v, is to have a housekeeping controller integrated into the primary-side ic (figure 16). this gives the highest efficiency, most cost effective a pplica t ions i n f or m a t ion figure 16. lt3752 forward controller with additional integrated housekeeping controller for primary-side and secondary-side bias v in r hislp r hsense v in v aux2 secondary-side bias v aux1 primary-side bias (connect to intv cc pin) 3753 f16 ? ? ? ltc3752 h out hi sense hfb gnd r2 r1 lt3753 3753f
29 for more information www.linear.com/lt3753 solution without the need for custom magnetics (limiting selection) or the need for an additional flyback controller ic. the lt3752 is a primary-side forward controller ic with an integrated housekeeping controller and can be easily substituted for the lt3753. for isolated solutions without a housekeeping controller, there are alternative methods for generating an auxiliary supply for primary-side and secondary-side circuitry. each method, however, will have trade-offs from the recom - mended housekeeping controller solution. primary-side auxiliary supply the lt3753 can operate without a primar y-side auxiliary supply since the v in pin has a wide operational range. the current required for all of the gate drivers (out, aout and sout) is supplied by an internal linear regulator con - nected between v in and intv cc . if the efficiency loss and/ or power dissipation and/or current drive capability of that internal linear regulator is a limiting factor in the forward converter design, then a primary-side bias (v aux1 ) can be generated to overdrive the intv cc pin (figure 17). v aux1 is generated using an extra winding (n aux ) from the main power transformer in combination with an inductor (l1) and two schottky diodes (d1, d2) to generate a buck-derived supply. a 1mh inductor will usually suffice and should be chosen to handle the maximum supply current required by intv cc . see also the section intv cc regulator bypassing and operation in the applications information section. secondary-side auxiliary supply there are various methods for generating an auxiliary supply to power secondary-side circuitry. the lt8311 synchronous rectifier controller and opto coupler driver ic can be powered in several ways including connection directly to v out . while this is the easiest method, there are various guidelines described in the lt8311 data sheet for powering its v in pin. in most cases a an auxiliary supply is a pplica t ions i n f or m a t ion v in v in ltc3753 intv cc d2 d1 c1 np v aux1 n aux out oc i sensep i sensen gnd 3753 f17 ? ? l1 figure 17. primary-side bias v aux1 (n aux , l1, d1, d2) lt3753 3753f
30 for more information www.linear.com/lt3753 the best approach. the following methods can be used to generate a bias (v aux2 ) to power secondary-side circuitry : (1) use a primar y-side forward controller with integrated housekeeping controller to generate a secondary-side bias (figure 16). (2) use a buck-derived bias using an extra winding from the main power transformer (similar method as figure 17, applied to secondary-side cir cuitry) (3) use a custom output inductor with overwinding (figure 18). (4) use a peak-charge circuit (figures 19 (a), (b), (c)). whichever method is used to create the auxiliar y supply for secondary-side circuitry, the forward converter should be tested to ensure the auxiliary supply is acceptable for a pplica t ions i n f or m a t ion figure 19. peak charge supply: (a) directly from sw, (b) for low v out applications, (c) for high v out applications figure 18. output inductor with overwinding supply voltage range, supply current requirements and behavior during converter power-up/down. primary-side power mosfet selection the selection of the primary-side n-channel power mosfet m1 is determined by the maximum levels expected for the drain voltage and drain current. in addition, the power losses due to conduction losses, gate driver losses and transition losses will lead to a fine tuning of the mosfet selection. if power losses are high enough to cause an unacceptable temperature rise in the mosfet then several mosfets may be required to be connected in parallel. the maximum drain voltage expected for the mosfet m1 follows from the equations previously stated in the active clamp topology sections: v ds (m1) = v in 2 /(v in C (v out ? n)) the mosfet should be selected with a bv dss rating ap- proximately 20% greater than the above steady state v ds calculation due to tolerances in duty cycle, load transients, voltage ripple on c cl and leakage inductance spikes. a mosfet with the lowest possible voltage rating for the application should be selected to minimize switch on re - sistance for improved efficiency. in addition, the mosfet should be selected with the lowest gate charge to further minimize losses. 3753 f18 n s main xfmr v out c out sw n p ? ? ? ? v aux2 n l2 n l1 3753 f19 n s main xfmr sw (a) (b) (c) v aux2 n p ? ? n s main xfmr sw v aux2 n p ? ? n aux ? n s main xfmr sw v aux2 n p ? ? n aux ? lt3753 3753f
31 for more information www.linear.com/lt3753 mosfet m1 losses at maximum output current can be approximated as : p m1 = p conduction + p gatedriver + p transition (i) p conduction = (n p /n s ) ? (v out /v in ) ? (n s /n p ? i out(max) ) 2 ? r ds(on) note: the on resistance of the mosfet, r ds(on) , in- creases with the mosfets junction temperature. r ds(on) should therefore be recalculated once junction tem - perature is known. a final value for r ds(on) and therefore p conduction can be achieved from a few iterations. (ii) p gatedriver = (q g ? intv cc ? f osc ) where, q g = gate charge (v gs = intv cc ) (iii) p transition = p turn_off + p turn_on ( 0 if zvs) (a) p turn_off = (1/2)i out(max) (n s /n p )(v in /1-d) (q gd /i gate ) ? f osc where, q gd = gate to drain charge i gate = 2a source/sink for out pin gate driver (b) p turn_on = (1/2)i out(max) (n s /n p )(v ds )(q gd /i gate ) ? f osc where, v ds = m1 drain voltage at the beginning of m1 turn on v ds typically sits between v in and 0v (zvs) during programmable timing t ao , negative i mag discharges m1 drain swp towards v in (figure 1). zvs is achieved if enough leakage inductance existsto delay the second - ary side from clamping m1 drain to v in and if enough energy is stored in l mag to discharge swp to 0v during that delay. (see programming active clamp switch timing: aout to out (t ao )). synchronous control (sout) the lt3753 uses the sout pin to communicate syn - chronous control information to the secondary side synchronous rectifier controller (figure 20). the isolating transformer (t sync ), coupling capacitor (c sync ) and resis - tive load (r sync ) allow the ground referenced sout signal to generate positive and negative signals required at the sync input of the secondary side synchronous rectifier controller. for the typical lt3753 applications operating with an lt8311, c sync is 220pf, r sync is 560 and t sync is typically a pulse pe-68386nl. figure 20. sout pulse transformer a pplica t ions i n f or m a t ion 3753 f20 c sync 220pf r sync 560 sync (secondary side controller) t sync sout (lt3753) 2 1 3 5 6 4 ? ? ? ? typically choose c sync between 220pf and 1nf. r sync should then be chosen to obey : (1) sout max /100ma r sync (l mag /c sync ) where, sout max = intv cc l mag = t syncs magnetizing inductance 100ma = sout gate driver minimum source current and (2) r sync ? c sync (C1) ? y/(ln (z/sout max )) lt3753 3753f
32 for more information www.linear.com/lt3753 where, y = sync minimum pulse duration (50ns; lt8311) z = |sync level to achieve y| (2v: l t8311) even though the lt3753 intv cc pin is allowed to be over driven by as much as 15.4v, sout max level should be de - signed to not cause t sync output to exceed the maximum ratings of the lt8311s sync pin. cost/space reduction : if discontinuous conduction mode (dcm) operation is acceptable at light load, the lt8311 has a preactive mode which controls the synchronous mosfets without t sync , c sync , r sync or the lt3753 timing resistors r tas , r tos (leave open). output inductor value the choice of output inductor value l out will depend on the amount of allowable ripple current. the inductor ripple current is given by: i l(ripple)(p-p) = ?i l = (v out /(l out ? f osc )) ? (1 C (v out /v in )(n p /n s )) the lt3753 allows very large ?i l values (low l out values) without the worry of insufficient slope compensationby allowing slope compensation to be programmed with an external resistor in series with the i sensep pin (see cur - rent sensing and programmable slope compensation). larger ?i l will allow lower l out , reducing component size, but will also cause higher output voltage ripple and core losses. for lt3753 applications, ?i l is typically chosen to be 40% of i out(max) . output capacitor selection the choice of output capacitor value is dependent on output voltage ripple requirements given by : ?v out ?i l (esr + (1/(8 ? f osc ? c out )) where, ?i l = output inductor ripple current i l(ripple)(p-p) esr = effective series resistance (of c out ) f osc = switching frequency c out = output capacitance this gives: c out = ?i l /(8 ? f osc ? ( ?v out C ?i l ? esr)) typically c out is made up of a low esr ceramic capacitor(s) to minimize ?v out . additional bulk capacitance is added in the form of electrolytic capacitors to minimize output voltage excursions during load steps. input capacitor selection the active clamp forward converter demands pulses of current from the input due to primary winding current and magnetizing current. the input capacitor is required to provide high frequency filtering to achieve an input voltage as close as possible to a pure dc source with low ripple voltage. for low impedance input sources and medium to low voltage input levels, a simple ceramic capacitor with low esr should suffice. it should be rated to operate at a worst case rms input current of : i cin(rms) = (n s /n p ) i out(max) /2 a small 1f bypass capacitor should also be placed close to the ic between v in and gnd. as input voltage levels increase, any use of bulk capacitance to minimize input ripple can impact on solution size and cost. in addition, inputs with higher source impedance will cause an increase in voltage ripple. in these applications it is recommended to include an lc input filter. the output impedance of the input filter should remain below the negative input impedance of the dc/dc forward converter. a pplica t ions i n f or m a t ion lt3753 3753f
33 for more information www.linear.com/lt3753 a pplica t ions i n f or m a t ion pcb layout / thermal guidelines for proper operation, pcb layout must be given special attention. critical programming signals must be able to co-exist with high dv/dt signals. compact layout can be achieved but not at the cost of poor thermal management. the following guidelines should be followed to approach optimal performance. 1. ensure that a local bypass capacitor is used (and placed as close as possible) between v in and gnd for the controller ic(s). 2. the critical programming resistors for timing (pins t ao ,t as ,t os ,t blnk , ivsec and rt) must use short traces to each pin. each resistor should also use a short trace to connect to a single ground bus specifically connected to pin 18 of the ic (gnd). 3. the current sense resistor for the forward converter must use short kelvin connections to the i sensep and i sensen pins. 4. high dv/dt lines should be kept away from all timing resistors, current sense inputs, comp pin, uvlo_vsec/ ovlo pins and the fb trace. 5. gate driver traces (aout, sout, out) should be kept as short as possible. 6. when working with high power components, multiple parallel components are the best method for spread - ing out power dissipation and minimizing temperature rise. in particular , multiple copper layers connected by vias should be used to sink heat away from each power mosfet . 7. keep high switching current pgnd paths away from signal ground. also minimize trace lengths for those high current switching paths to minimize parasitic inductance. lt3753 3753f
34 for more information www.linear.com/lt3753 a pplica t ions i n f or m a t ion figure 21. 36v to 72v, 5v/20a 100w active clamp isolated forward converter r4 44.2k r3 1.87k r5 14.7k r7 57.6k r6 30.1k r9 100k r8 100k v + gnd-f gnd-s coll c11 3.3nf r22 34.8k ref lt1431 1k r13 r12 0.012 m1 m3 m4 m2 r14 10k d1 r11 100 ps2801-1 1k r10 2.2nf 250v t1: champs g45r2-0209 l1: champs pqi2050-3r3 d1: bas516 d2: central semi. cmhz5229b c2 1f c3 22nf c4 4.7f 25v c10 1f 10v c9 22f 10v r18 1k v out d2 c13 47f 10v v out 5v 20a c12 560f 10v 3753 f21 c14 1f t ao t as t os t blnk ivsec rt ss1 ss2 fb comp intv cc sout i sensen i sensep out v in aout oc r2 1.96k r1 105k uvlo_v sec lt3753 sync c5 100nf irf6217 t1 9:2 c7 68nf 250v bsc0902nsi bsc0902nsi bsc190n15ns3 l1 3.3h r20 137k r21 137k + ?? c1 4.7f 100v 3 v in 36v to 72v gnd ovlo r19 100 c8 4.7nf c6, 250v 0.22f r15 200 r16 5 r17 5 load current (a) 3753 f21a 20 1210 16 1814 0 efficiency (%) 96 94 92 86 90 88 42 86 36v in 48v in 72v in efficiency vs load current lt3753 3753f
35 for more information www.linear.com/lt3753 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage descrip t ion please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. 4.75 (.187) ref fe38 (ab) tssop rev b 0910 0.09 ? 0.20 (.0035 ? .0079) 0 ? 8 0.25 ref 0.50 ? 0.75 (.020 ? .030) 4.30 ? 4.50* (.169 ? .177) 1 19 pin numbers 23, 25, 27, 29, 31, 33 and 35 are removed 20 ref 9.60 ? 9.80* (.378 ? .386) 38 1.20 (.047) max 0.05 ? 0.15 (.002 ? .006) 0.50 (.0196) bsc 0.17 ? 0.27 (.0067 ? .0106) typ recommended solder pad layout 0.315 0.05 0.50 bsc 4.50 ref 6.60 0.10 1.05 0.10 4.75 ref 2.74 ref 2.74 (.108) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc fe package package variation: fe38 (31) 38-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1865 rev b) exposed pad variation ab lt3753 3753f
36 for more information www.linear.com/lt3753 ? linear technology corporation 2014 lt 0414 ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/lt3753 3753 f22 lt3753 uvlo_vsec ovlo ivsec rt tos tblnk tao tas gnd ss1 ss2 intv cc aout fb sync s out r4 71.5k c4 1f c3 0.47f v in 18v to 72v v in r2 5.9k r3 1.82k r5 31.6k 240khz r7 34k comp isensen oc out isensep r6 49.9k c10 2.2f 100v ?? c9 100nf c6 4.7f r13, 2k r12 6m r11 100 c7 1f r10 1k r8 100k r9 100k r22 124k lt8311 fsw csw csp cg csn opto gnd comp sync pmode ss fb v in intv cc pgood timer v out 12v/8a v out l1 6.8h d2 r19, 1.78k r20, 1.5k fg r16, 2k r25 100k r24 20k r26 11.3k c19 22f 2 r17, 2k r18, 1.78k c20 470f c18 68pf c12 15nf r21 2.94k c14 1f c15 4.7f c16 2.2f c17 2.2nf r14 10k c11 100nf 4:4 t1 r23 100k 2.2nf ps2801-1 c5 10pf + c1 4.7f 3 r1 100k d1 d3 t1: champs g45r2-0404.04 l1: champs pqr2050-6r8 m1: infineon bsc077n12ns3 m2: international rectifier irf6217 m3: fairchild semi. fdms86101dc m4: infineon bsc077n12ns3 d2: central semi. cmmr1u-02 d3: diodes inc. sbr1u150sa m3 m1 m4 m2 r ela t e d p ar t s typical a pplica t ion part number description comments lt3752/lt3752-1 active clamp synchronous forward controllers with internal housekeeping controller ideal for medium power 24v, 48v and up to 400v input applications lt8311 preactive secondary synchronous and opto control for forward converters optimized for use with primary-side lt3752/-1, lt3753 and lt8310 controllers ltc3765/ltc3766 synchronous no-opto forward controller chip set with active clamp reset direct flux limit, supports self starting secondary forward control ltc3722/ltc3722-2 synchronous full bridge controllers adaptive or manual delay control for zero voltage switching, adjustable synchronous rectification timing lt3748 100v isolated flyback controller 5v v in 100v, no opto flyback , msop-16 with high voltage spacing lt3798 off-line isolated no-opto flyback controller with active pfc v in and v out limited only by external components figure 22. 18v to 72v, 12v/8a active clamp isolated forward converter efficiency and power loss load current (a) 0 efficiency (%) power loss (w) 96 94 92 86 90 88 14 12 10 0 8 6 4 2 2 3753 f22a 10 6 8 4 v in = 48v lt3753 3753f

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